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Features
Preliminary
EM488M3244VBC
256Mb (2Mx4Bankx32) Synchronous DRAM
Description
The EM488M3244VBC is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages: BGA-90B (13mmx8mm).
* Fully Synchronous to Positive Clock Edge * Single 2.7V ~ 3.6V Power Supply * LVCMOS Compatible with Multiplexed Address * Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page * Programmable CAS Latency (C/L) - 2 or 3 * Data Mask (DQM) for Read / Write Masking * Programmable Wrap Sequence - Sequential (B/L = 1/2/4/8/full Page) - Interleave (B/L = 1/2/4/8) * Burst Read with Single-bit Write Operation * Deep Power Down Mode. * Auto Refresh and Self Refresh * Special Function Support. - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) * Programmable Driver Strength Control - Full Strength or 1/2, 1/4 of Full Strength * 4,096 Refresh Cycles / 64ms (15.625us)
Ordering Information
Part No
EM488M3244VBC-75F EM488M3244VBC-75FE
Organization
8M X 32 8M X 32
Max. Freq
133MHz @CL3 133MHz @CL3
Package
BGA-90B BGA-90B
Grade
Commercial
Pb
Free
Extend temp. Free
* EOREX reserves the right to change products or specification without notice.
May. 2007 1/19
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Pin Assignment
1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 2 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS
Preliminary
EM488M3244VBC
3 A B C D E F G H J K L M N P R VDD
7 DQ23
8 DQ21 DQ19
9
VDDQ DQ22 DQ17 NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 VDDQ VDD
VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS /WE DQ7 DQ5 DQ3 VSSQ DQ0
VDDQ VDDQ VSSQ VDD A1 A11 /RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
90ball BGA / (13mm x 8mm)
May. 2007 2/19
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Pin J1 J8 Name CLK /CS
Preliminary
EM488M3244VBC
Pin Description (Simplified)
Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when "H" and deactivates when "L". CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS "L". Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers.
J2
CKE
G8,G9,F7,F3,G1, G2,G3,H1,H2,J3, G7,H9
A0~A11
J7,H8 J9
BA0,BA1 /RAS
K7
/CAS
K8 K9,K1,F8,F2 R8,N7,R9,N8,P9, M8,M7,L8,L2,M3, M2,P1,N2,R1,N3, R2,E8,D7,D8,B9, C8,A9,C7,A8,A2, C3,A1,C2,B1,D2, D3,E2 A7,F9,L7,R7/ A3,F1,L3,R3 B2,B7,C9,D9,E1, L1,M9,N9,P2/B8, B3,C1,D1,E9,L9, M1,N1,P8 E3,E7,H3,H7,K2, K3
May. 2007
/WE DQM0~DQM3
DQ0~DQ31
(Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM.
VDD/VSS
(Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device.
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VDDQ/VSSQ
NC
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Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD
Preliminary
EM488M3244VBC
Item Input, Output Voltage Power Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation
Rating -0.3 ~ +4.6 -0.3 ~ +4.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 1
Units V V C C W
IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=3.3V, f=1MHz, TA=25C)
Symbol CCLK CI CO Parameter Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance Min. 4 4 3 Typ. Max. 8 8 5 Units pF pF pF
Recommended DC Operating Conditions (TA=0C ~70C)
Symbol VDD VDDQ VIH Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Logic High Voltage Min. 2.7 2.7 2.2 -0.3 Typ. 3.3 3.3 Max. 3.6 3.6 VDD+0.3 0.5 Units V V V V
VIL Input Logic Low Voltage Note: * All voltages referred to VSS. * VIH (max.) = 5.6V for pulse width 3ns * VIL (min.) = -2.0V for pulse width 3ns
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Symbol ICC1 ICC2P ICC2PS ICC2N Parameter Operating Current
(Note 1)
Preliminary
EM488M3244VBC
Recommended DC Operating Conditions
(VDD=3.3V0.3V, TA=0C ~70C , -25C ~ +85C) Test Conditions Burst length=1, tRCtRC(min.), IOL=0mA, One bank active CKEVIL(max.), tCK=15ns CKEVIL(max.), tCK= CKEVIL(min.), tCK=15ns, /CSVIH(min.) Input signals are changed one time during 30ns CKEVIL(min.), tCK= , Input signals are stable CKEVIL(max.), tCK=15ns CKEVIL(max.), tCK= CKEVIL(min.), tCK=15ns, /CSVIH(min.) Input signals are changed one time during 30ns CKEVIL(min.), tCK= , Input signals are stable tCCD2CLKs, IOL=0mA tRCtRC(min.) CKE0.2V 0.4 Max. 80 1 1 20 Units mA mA mA mA
Precharge Standby Current in Power Down Mode
Precharge Standby Current in Non-power Down Mode
ICC2NS ICC3P ICC3PS ICC3N Active Standby Current in Power Down Mode
2 10 2 40
mA mA mA mA
Active Standby Current in Non-power Down Mode
ICC3NS ICC4 ICC5 ICC6 Operating Current (Burst (Note 2) Mode) Refresh Current
(Note 3)
20 100 180
(Note 4)
mA mA mA mA
Self Refresh Current
*All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) Note 4: Standard power version.
Recommended DC Operating Conditions (Continued)
Symbol IIL IOL VOH VOL
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Parameter Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage
Test Conditions 0VIVDDQ, VDDQ=VDD All other pins not under test=0V 0VOVDDQ, DOUT is disabled IO=-2mA IO=+2mA
Min. -0.5 -0.5 2.4
Typ.
Max. +0.5 +0.5 0.4
Units uA uA V V
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Block Diagram
Preliminary
EM488M3244VBC
Auto/Self Refresh Counter
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 S/A & I/O Gating Col. Decoder Data Out DOi Data In DQM
Memory Array
Write DQM Control
BA0 BA1 Col. Add. Buffer Read DQM Control
Mode Register Set
Col. Add. Counter Burst Counter
Timing Register
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
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(VDD=3.3V0.3V, TA=0C ~70C) Item Output Reference Level Output Load Input Signal Level
Preliminary
EM488M3244VBC
AC Operating Test Conditions
Conditions 0.5*VDDQ / 0.5* VDDQ See diagram as below 2.4V/0.4V 1ns VDDQ/2
Transition Time of Input Signals Input Reference Level
AC Operating Test Characteristics
(VDD=3.3V0.3V, TA=0C ~70C, -25C ~ +85C) Symbol tCK tAC tCH tCL tOH tHZ tLZ tIH tIS Parameter Clock Cycle Time Access Time form CLK CLK High Level Width CLK Low Level Width Data-out Hold Time Data-out High Impedance (Note 5) Time Input Hold Time Input Setup Time CL=3 CL=2 CL=3 CL=2 1.5 1.5 2.5 CL=3 CL=2 CL=3 CL=2 3 3 2.2 2.2 7 9 -7.5 Min. Max. 7.5 10 6 8 Units ns ns ns ns ns ns ns ns ns
Data-out Low Impedance Time
* All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels.
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Symbol tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL tROH tREF Parameter
Preliminary
EM488M3244VBC
AC Operating Test Characteristics (Continued)
(VDD=3.3V0.3V, TA=0C ~70C, -25C ~ +85C) -7.5 Min. Max. 67.5 45 22.5 22.5 15 1 2 1 3 2 64 100K Units ns ns ns ns ns CLK CLK CLK CLK ms
ACTIVE to ACTIVE Command (Note 6) Period ACTIVE to PRECHARGE (Note 6) Command Period PRECHARGE to ACTIVE (Note 6) Command Period ACTIVE to READ/WRITE Delay (Note 6) Time ACTIVE(one) to ACTIVE(another) (Note 6) Command READ/WRITE Command to READ/WRITE Command Date-in to PRECHARGE Command Date-in to BURST Stop Command Data-out to High CL=3 Impedance from CL=2 PRECHARGE Command Refresh Time (4,096 cycle)
* All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user's specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register.
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Simplified State Diagram
Preliminary
EM488M3244VBC
SE LF E CK
h
Wr i te
wit
May. 2007 9/19
PR E
SE LF
Ex it
E CK
ACT
T BS ad e R
ad Re wit h E PR
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BA1 BA0 A11 A10 A9 Operation Mode
Preliminary
EM488M3244VBC
Address Input for Mode Register Set
A8 A7 A6 A5 A4 A3 BT A2 A1 A0 CAS Latency Burst Length
Burst Length Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Interleave 1 2 4 8 Reserved Reserved Reserved Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Burst Type Interleave Sequential
A3 1 0
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
BA1 0 0
BA0 0 0
A11 0 0
A10 0 0
A9 0 1
A8 0 0
A7 0 0
Operation Mode Normal Burst Read with Single-bit Write
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Burst Type (A3)
Burst Length 2 A2 X X X 4 X X X 0 0 0 8 0 1 1 1 1 A1 X X 0 0 1 1 0 0 1 1 0 0 1 1
Preliminary
EM488M3244VBC
A0 0 0 0 1 0 1 0 1 0 1 0 1 0 1
Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456
Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 -
Full Page* n n n Cn Cn+1 Cn+2...... * Page length is a function of I/O organization and column addressing x32 (CA0 ~ CA8): Full page = 512bits
May. 2007 11/19
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Preliminary
EM488M3244VBC
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
BA1 1
BA0 0
A11 0
A10 0
A9 0
A8 0
A7 0
A6 DS
A5
A4 0
A3 0
A2
A1 PASR
A0
Self Refresh Coverage All Banks Two Banks (BA1=0) One Bank (BA0=BA1=0) Reserved Reserved Half of One Bank (BA0=BA1=0 ,Row Address MSB=0) Quarter of One Bank (BA0=BA1=0 ,Row Address 2 MSB=0) Reserved
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Driver Strength full 1/2 Strength 1/4 Strength Reserved
A6 0 0 1 1
A5 0 1 0 1
BA1 0 1
MRS Normal EMRS
May. 2007 12/19
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Output Drive Strength Partial Array Self Refresh
Preliminary
EM488M3244VBC
The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected.
In EMRS setting ,memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self-refresh.
1. Command Truth Table
Command Ignore Command No Operation Burst Stop Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks Symbol DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL CKE n-1 n HX H H H H H H H H H X X X X X X X X X /CS H L L L L L L L L L /RAS X H H H H H L L L L /CAS X H H L L L H H H H /WE X H L H H L H H L L BA0, BA1 X X X V V V V V V X A10 X X X L H L H V L H L A11, A9~A10 X X X V V V V V X X V
Mode Register Set MRS HX L L L L L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
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2. DQM Truth Table
Command Data Write/Output Enable Data Mask/Output Disable
Preliminary
EM488M3244VBC
Symbol ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL
CKE n-1 H H H H H H H H H H n X X X X X X X X X X
/CS H L L L L L L L L L L
Upper Byte Write Enable/Output Enable Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks
Mode Register Set MRS H X H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
3. CKE Truth Table
Item Activating Any Clock Suspend Idle Idle Self Refresh Idle Command Clock Suspend Mode Entry Clock Suspend Mode Clock Suspend Mode Exit CBR Refresh Command Self Refresh Entry Self Refresh Exit Power Down Entry REF SELF Symbol CKE n-1 n H L L L L H H L L H H H L H H L /CS X X X L L L H X /RAS X X X L L H X X X /CAS X X X L L H X X X /WE X X X H H H X X X Addr. X X X X X X X X X
Power Down Power Down Exit L H X Remark H = High level, L = Low level, X = High or Low level (Don't care)
May. 2007 14/19
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Current State /CS
H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L L L L L L L H H L L L H L H L
Preliminary
EM488M3244VBC
Action Nop or power down Nop or power down ILLEGAL
(Note 9) (Note 9) (Note 8) (Note 8)
4. Operative Command Table (Note 7)
/R
X H H H L L L L X H H H L L L L X H H H L L L L L X H H H
/C
X H L L H H L L X H L L H H L L X H H L L H H L L X H H L
/W
X X H L H L H L X X H L H L H L X H L H L H L H L X H L H
Addr.
X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code
Command
DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
ILLEGAL Row activating Nop Refresh or self refresh
(Note 10)
Mode register accessing Nop Nop (Note 11) Begin read: Determine AP Begin write: Determine AP ILLEGAL
(Note 9) (Note 12) (Note 11)
Pre-charge
ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, new read: (Note 13) Determine AP Terminate burst, start write: (Note 13, 14) Determine AP ILLEGAL
(Note 10) (Note 9)
(Note 10)
Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read: (Note 13, 14) Determine AP 7, 8 Terminate burst, new write: (Note 13) Determine AP 7 ILLEGAL
(Note 15) (Note 9)
Terminate burst, pre-charging
ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care)
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Current State /CS
H L Read with AP L L L L L L L H L Write with AP L L L L L L L H L L L Pre-charging L L L L L H L L L Row Activating L L L L L
Preliminary
EM488M3244VBC
4. Operative Command Table (Continued) (Note 7)
/R
X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
/C
X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L
/W
X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Action Continue burst to end Pre-charging Continue burst to end Pre-charging ILLEGAL (Note 9) ILLEGAL ILLEGAL ILLEGAL
(Note 9) (Note 9) (Note 9)
ILLEGAL ILLEGAL ILLEGAL Burst to end Write recovering with auto pre-charge Continue burst to end Write recovering with auto pre-charge ILLEGAL (Note 9) ILLEGAL ILLEGAL ILLEGAL
(Note 9) (Note 9) (Note 9)
ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL (Note 9) ILLEGAL ILLEGAL
(Note 9) (Note 9)
ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter idle after tRCD Nop Enter idle after tRCD ILLEGAL (Note 9) ILLEGAL ILLEGAL ILLEGAL
(Note 9) (Note 9, 16) (Note 9)
ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
May. 2007 16/19
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Current State /CS
H L L L L L L L L H L L L L L L L L H L L L L H L L L L
Preliminary
EM488M3244VBC
4. Operative Command Table (Continued) (Note 7)
/R
X H H H H L L L L X H H H H L L L L X H H L L X H H H L
/C
X H H L L H H L L X H H L L H H L L X H L H L X H H L X
/W
X H L H L H L H L X H L H L H L H L X X X X X X H L X X
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS
Action Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL Start read, Determine AP (Note 14) New write, Determine AP ILLEGAL
(Note 9) (Note 9)
Write Recovering
Write Recovering with AP
ILLEGAL ILLEGAL ILLEGAL Nop Enter pre-charge after tDPL Nop Enter pre-charge after tDPL Nop Enter pre-charge after tDPL (Note 9, 14) ILLEGAL ILLEGAL
(Note 9) (Note 9)
Refreshing
Mode Register Accessing
ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if tRCD is not satisfied. Note 12: Illegal if tRAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy tDPL. Note 16: Illegal if tRRD is not satisfied.
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Current State CKE n-1 n
H Self Refresh L L L L L H H H H H H H H H Power Down L L H H H H H H H H H H L Row Active H L H Any State Other than Listed above H L L X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L
Preliminary
EM488M3244VBC
5. Command Truth Table for CKE
/CS
X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X
/R
X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X
/C
X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X
/W
X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X
Addr.
X X X X X X X X X X X X X X X X X
Action INVALID, CLK(n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down Idle Maintain power down mode Refer to operations in Operative Command Table
Self Refresh Recovery
X Op-Code
Refresh Refer to operations in Operative Command Table
Both Banks Idle
X Op-Code X X X
X X X
Self refresh Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table Begin clock suspend next cycle
(Note 18)
(Note 17)
Exit clock suspend next cycle Maintain clock suspend Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Notes 18: Must be legal command as defined in Operative Command Table
May. 2007 18/19
www.eorex.com
eorex
Package Description
Preliminary
EM488M3244VBC
May. 2007 19/19
www.eorex.com

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